Design of low voltage cmos tristate buffer

Nurul Huda, Binti Zulkifli. (2010) Design of low voltage cmos tristate buffer. [Final Year Project Report] (Unpublished)

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Abstract

CMOS tristate buffer are widely used in electronic systems. As the increasing of its usage, it is also demanding that the buffer is operating in high speed. So the high speed CMOS tristate buffer is designed. High speed systems are easy to be implemented, but for a high speed with low voltage system are difficult to achieve. As the voltage used is low, the power consumption will be also low. The objective of this project is to design a low voltage tristate buffer that can drive a larger capacitive load. The problem is how to maintain the throughput while in most cases, lowering voltage of the system will lowering the system speed too. By applying transistor sizing to the high speed circuit, the supply voltage used in this circuit is lowered from the high speed design. The chosen optimum value used for supply voltage is 1.6 V while chosen value for capacitive load is 10 pF. As the value of the supply voltage is getting lower, it is shown at the same time that the Power Delay Product and Energy Delay Product also decreasing while maintained the high speed.

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