SOFT ERROR MITIGATION IN MEMORY SYSTEM

Norhuzaimin, Julai and FARHANA, MOHAMAD ABDUL KADIR and Shamsiah, Suhaili (2023) SOFT ERROR MITIGATION IN MEMORY SYSTEM. Journal of Engineering Science and Technology, 18 (2). pp. 862-879. ISSN 1823-4690

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Abstract

Technology downscaling has increased the sensitivity of circuitry to being corrupted by single event upsets. To provide more solutions for the issue, a method of error detection and correction is provided in this study. The double exponential model was used to simulate the single event upset current transient. The amplitudes of the transient current from the single event upset were varied until a change in logic value is achieved. A single rail with inverter latch (SIL) circuit configuration is injected in three vulnerable nodes to formulate their respective soft error sensitivities, with the parameters of temperature and voltage supply varied to observe their effects on the critical charge of each node. The temperatures were ranged from -50ºC to 200 ºC, while the supply voltage was varied from 0.7 V to 1.5 V. Decreases in temperature from the range of 200ºC to -50ºC cause the critical charge to increase. Critical charge increases with voltage supply increase from 0.7 V to 1.5 V. A shadow latch was implemented in Cadence and Quartus for error detection and correction. The shadow latch was able to successfully detect the presence of an error and restore the original data from voltages of 0.8 V to 1.2 V.

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