Analysis of Gate Poly Delayering in SOI Wafer

Shahrol, Mohamaddan and Handie, Ahmataku and Emilda, Warren and Mahshuri, Yusof and Aidil Azli, Alias and Nor Hasmaliana, Abdul Manas and Kuryati, Kipli (2018) Analysis of Gate Poly Delayering in SOI Wafer. Journal of Telecommunication, Electronic and Computer Engineering, 10 (1-12). pp. 85-87. ISSN 2180-1843

PDF Analysis of Gate Poly Delayering in SOI Wafer (abstract).pdf Download (245kB)

Abstract

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS). Thus, this method was tested on SOI Wafer to analyze the effect. The experiment was conducted by selecting small, thin and dense gate polysilicon such as in Static Random Access Memory (SRAM) cells. The result shows that high concentration of HF is not suitable for SOI since HF will etch Interlayer Dielectric (ILD) all the way down to Buried Oxide (BOX) and leave top silicon unattached. As a result, top silicon structure was peeled off or damaged. The result was not promising since the top silicon is crucial part as it holds information to discover physical cause of failure.

Actions (For repository members only: login required)

View Item