Raynold Gerijih Belasap Anak David, - (2022) TOPOLOGICAL DESIGN EXPLORATION FOR 10×10 MESH WIRELESS NETWORK-ON-CHIP. [Final Year Project Report] (Unpublished)

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Wireless Network on Chip is an innovative technique to resolving latency and power consumption limitations in Network-on-Chip (NoC). This project targets to improve the performance of the Wireless Network on Chip (WiNoC) on different radio hub location for 10×10 MESH topology. As WiNoC has gotten bigger as a communication technology, it has encountered issues with topological performance that must be addressed. The system with high latency will affect the network throughput. Thus, the power consumption by system might get higher due to many workloads. The power consumption model and the system interference model have been offered as methods for achieving the desired topology generation. By utilizing the cycle accurate on chip simulator (Noxim), the experimental simulation compares three topologies with different placements for the radio hub in order to assess how well each one performs in terms of latency, network throughput, and energy consumption. By this experiment, the best topology is the 4-hub topology (WiNoC).

Item Type: Final Year Project Report
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Academic Faculties, Institutes and Centres > Faculty of Engineering
Depositing User: John
Date Deposited: 02 Sep 2022 03:13
Last Modified: 02 Sep 2022 03:13

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