Power Optimization for Mesh Network-on-Chip Architecture: Multilevel Network Partitioning Approach

Asrani, Lit and Siti Kudnie, Sahari and R., Spawi and Shamsiah, Suhaili and Dayang Nur Salmi Dharmiza, Awang Salleh and Ana Sakura, Zainal Abidin and A. F., Hassan (2013) Power Optimization for Mesh Network-on-Chip Architecture: Multilevel Network Partitioning Approach. In: EnCon 2013, 6th Engineering Conference "Energy and Environment", 2-4 July 2013, Kuching Sarawak.

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Abstract

This paper presents a power optimization for mesh Network-on-Chip (NoC) architecture by using Multilevel Network Partitioning approach. Power consumption is reduced by re-dividing the large networks into few smaller partitions. This approach assigns excessively communicated Intellectual Property (IP) cores into the same portion that result the minimal average inter-core distance. The efficiency of this methodology is verified through a System-on-Chip (SoC) application known as Video Object Plan Decoder (VOPD). Experimental results show a promising improvement of 16.59% in the power consumption.

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