Khadijah binti, Usaini (2004) Design of buffer to drive large capacitive load with minimum delay. [Final Year Project Report] (Unpublished)
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Abstract
The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A.
Item Type: | Final Year Project Report |
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Additional Information: | Project Report (BSc.) - Universiti Malaysia Sarawak, 2004. |
Uncontrolled Keywords: | UNIMAS, Universiti Malaysia Sarawak, research, undergraduate, engineering, cascade of inverters, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, IPTA, education |
Subjects: | T Technology > TJ Mechanical engineering and machinery T Technology > TK Electrical engineering. Electronics Nuclear engineering |
Divisions: | Academic Faculties, Institutes and Centres > Faculty of Engineering Faculties, Institutes, Centres > Faculty of Engineering |
Depositing User: | Karen Kornalius |
Date Deposited: | 21 May 2014 02:26 |
Last Modified: | 26 Oct 2023 07:40 |
URI: | http://ir.unimas.my/id/eprint/2805 |
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