Husin, M.H. and Leong, S.Y. and Sabri, M.F.M. (2013) Built in self test for RAM using VHDL. IEEE Colloquium on Humanities, Science and Engineering (CHUSER), 2012. ISSN ISBN: 978-1-4673-4617-7
|
PDF
Built in self test for RAM Using VHDL.pdf Download (398kB) | Preview |
Abstract
This project emphasized mainly on software analysis. Modelsim-Altera 6.4a is the software that used to generate every single module of the Built-in-Self-Test (BIST) for Random access Memory (RAM) architecture. There are three key things to be concern in the BIST for RAM which is the Test Pattern Generator (TPG), Output Response Analysis (ORA) and RAM. The output of counter which is a type of TPG is analyzed to provide a pattern for March test algorithm. At the mean time, the ORA compare the output from decoder and the RAM output itself which modeled under the theory of numerical autonomy of error vectors from the circuit under test. The output of ORA, the comparator, will show pass or fail for faulty detection of RAM. The system has been successfully developed and vector waveform is used to examine the result of the system. From the result obtained, it showed that the system is working as expected with satisfactory result.
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | ORA, BIST, RAM, TPG, integrated circuit reliability, integrated circuit testing, numerical analysis, research, Universiti Malaysia Sarawak, unimas, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, ipta, education |
| Subjects: | T Technology > TA Engineering (General). Civil engineering (General) |
| Divisions: | Academic Faculties, Institutes and Centres > Faculty of Engineering Faculties, Institutes, Centres > Faculty of Engineering |
| Depositing User: | Karen Kornalius |
| Date Deposited: | 14 Jun 2017 07:22 |
| Last Modified: | 14 Jun 2017 07:22 |
| URI: | http://ir.unimas.my/id/eprint/16645 |
Actions (For repository members only: login required)
 |
View Item |
