High Gain of 3.1-5.1 GHz CMOS Power Amplifier for Direct Sequence Ultra-Wideband Application

Sapawi, R. and Asyraf, A.N. and Mohamad Hasnul, D.H.A. and Sahari, S.K. and Masra, S.M.W. and Kipli, K. and Julai, N. and Junaidi, Nazreen and Salleh, D.N.S.A and Murad, S.A.Z. (2017) High Gain of 3.1-5.1 GHz CMOS Power Amplifier for Direct Sequence Ultra-Wideband Application. Journal of Telecommunication, Electronic and Computer Engineering, 8 (12). pp. 99-103. ISSN 2289-8131

Preview

PDF High Gain of 3.1-5.1 GHz CMOS Power Amplifier for Direct Sequence Ultra-Wideband Application (abstract).pdf Download (223kB) | Preview

Abstract

This paper presents the design a power amplifier (PA) for direct sequence ultra-wideband applications using 0.13 μm CMOS technology operating in a low band frequency of 3.1 GHz to 5.1 GHz. Current-reused technique is employed at the first stage to increase the gain at the upper end of the desired band. Cascaded common source configuration with shunt peaking inductor at the second stage helps to enhance the wideband frequency while increasing the gain approximately twice the performance. The simulation results specify that high gain of 20.3 dB with ± 0.8 dB flatness, group delay variation of ±121.3 ps, and good input return loss and output return loss is obtained over desired working band. The proposed PA achieves power consumption of 27.3 mW.

Actions (For repository members only: login required)

View Item