Shamsiah, Binti Suhaili and Takahiro, Watanabe (2016) High throughput evaluation of SHA-1 implementation using unfolding transformation. ARPN Journal of Engineering and Applied Sciences, 11 (5). pp. 3350-3355. ISSN 1819-6608
Full text not available from this repository.Abstract
Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C4. In this paper, two types of design are proposed, namely SHA-1 and SHA-1unfolding. The maximum frequency of SHA-1 design is 274.2 MHz which is higher than SHA-1 unfolding that has the maximum frequency of only 174.73 MHz. However, this leads to a high throughput of the SHA1 unfolding design with 2236.54 Mbps. Besides, both designs provide a small area implementation on Arria II that requires only 423 and 548 Combinational ALUTs, 693 and 907 total register, respectively
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | maximum frequency, FPGA, HDL, SHA-1,unimas, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, ipta, education, research, Universiti Malaysia Sarawak |
| Subjects: | T Technology > TA Engineering (General). Civil engineering (General) |
| Divisions: | Academic Faculties, Institutes and Centres > Faculty of Engineering Faculties, Institutes, Centres > Faculty of Engineering |
| Depositing User: | Saman |
| Date Deposited: | 25 May 2016 03:09 |
| Last Modified: | 17 Feb 2017 00:56 |
| URI: | http://ir.unimas.my/id/eprint/12162 |
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