Improving on board integrated circuits testing using one shared test access port and single bidirectional test data line

Salim Ahmad, Jayousi (2015) Improving on board integrated circuits testing using one shared test access port and single bidirectional test data line. PhD thesis, Universiti Malaysia Sarawak, (UNIMAS).

PDF (Please get the password by email to repository@unimas.my , or call ext: 082-583914/3973/3933) Salim.pdf Restricted to Registered users only Download (9MB)

Abstract

Traditional test and measurement equipment that relies on connecting external probes is no longer possible given the state of the art of today’s shrinking printed circuit boards (PCBs). Since probing is extremely difficult, other methods must then be explored. A new and reliable approach for testing PCBs is presented in this research that provides an elegant solution for this problem. The approach is developed based on IEEE Std. 1149.1 for testing and debugging. It defines the architecture for testing modern integrated circuits (ICs) over PCBs without external probing. PCBs compliant with this approach will contain one shared access interface to access testing logic. Chips compliant with this technique will contain bypass registers only, whereas the chips that are compliant with IEEE Std. 1149.1 contain four types of registers. The shared access interface, which is called test access port (TAP), has a universal serial bus (USB) port interface. The chips over the PCB are connected with the shared TAP using the star topology. Only one bidirectional data line was used to connect each IC. The TAP has been totally controlled by an open source and user friendly software that has been developed using the Arduino application. The software is able to access the IC logic and to generate automatic test patterns. It handled the details of the logic such that users can focus on the actual testing without having to worry about or needing to know the implementation details at chip level. The logic circuit of this design has been simulated and the hardware prototype has been built successfully. The new design has the distinct feature of being less complex, less expensive, and more reliable than those compliant with IEEE Std. 1149.1. The proposed method succeeded in performing 98% of the scan testing on logical ICs, whereas the fault coverage was 96% for the same ICs.

Actions (For repository members only: login required)

View Item