Designing uart by using gate-lever implementation

Iffah, Mohamed @ Mohamad Saim (2006) Designing uart by using gate-lever implementation. [Final Year Project Report] (Unpublished)

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Abstract

Universal Asynchronous Receiver/ Transmitter (UART) is very popular among serial communication devices especially between devices that are separated by long distances . The UART consists of two main circuits which is a transmitter, that transmits parallel - to - serial data and a receiver which is receives serial - to - parallel data. The main purpose of this project is to design a full UART module by using gate - level implementation. The softw are used is Altera MAX+PLUS II and it is easily adapte d to specific design needs. The fi r st task is to design a control path also known as Finite State Machine (FSM) and data path for T ransmitter and Receiver Module. Boolean equations has been derived from Karnaugh Map are needed to minimize the usage of logi c gate in the FSM circuit. Then Data Register, Shift Register, Parity Generator and Error Checker for both modules are designed by using combinational and sequential logic design. The final task is to combine both modules as a full UART design. Some tests and analysi s had been done on transmitted and received data, parity error, framing error and overrun error to ensure that each component is working properly .

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