Implementation of Verilog HDL in Calculator Design with FPGA Simulation

Shamsiah, Suhaili and Kayle Jacqueline, Kumar and Norhuzaimin, Julai and Maimun, Huja Husin and Mohd Faizrizwan, Mohd Sabri and Asrani, Lit (2020) Implementation of Verilog HDL in Calculator Design with FPGA Simulation. 2020 13th International UNIMAS Engineering Conference (EnCon).

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Official URL: https://ieeexplore.ieee.org/document/9299337

Abstract

A calculator is a device that can be found in daily life. This paper proposed the design of a calculator using Verilog HDL. A series of synthesizable Verilog code was created and simulated on Quartus II 15.0. The design of an 8-bit calculator can solve mathematical operations such as addition, subtraction, multiplication, division, square and cube functions, square root and factorial. This calculator consists of eight-digit numbers. In this paper, among the family devices in Altera, Cyclone V was used to perform the simulation process. The outputs are shown in the RTL viewer and waveform simulation of the calculator design. The implementation of a calculator was successfully designed using Verilog HDL in terms of digit numbers and the operation of the calculator function.

Item Type: Article
Uncontrolled Keywords: Calculator, Verilog, Digital design, Mathematical operation
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Academic Faculties, Institutes and Centres > Faculty of Engineering
Depositing User: Suhaili
Date Deposited: 30 Dec 2020 06:14
Last Modified: 30 Dec 2020 06:14
URI: http://ir.unimas.my/id/eprint/33604

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