Design of Completion Detectors in Asynchronous Communication System

Norhuzaimin, Julai and Shamsiah, Binti Suhaili and Yonis M, Yonis Buswig (2020) Design of Completion Detectors in Asynchronous Communication System. International Journal of Innovative Technology and Exploring Engineering (IJITEE), 9 (3). pp. 3329-3334. ISSN 2278-3075

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Abstract

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation

Item Type: E-Article
Uncontrolled Keywords: Asynchronous, converter, completion detector, Quartus II, unimas, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, ipta, education, research, Universiti Malaysia Sarawak.
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Academic Faculties, Institutes and Centres > Faculty of Engineering
Depositing User: Yonis Buswig
Date Deposited: 17 Jan 2020 02:45
Last Modified: 17 Jan 2020 02:45
URI: http://ir.unimas.my/id/eprint/28756

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