Designing 8-Bit multiplier

Yee, M.F (2006) Designing 8-Bit multiplier. [Final Year Project Report] (Unpublished)

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Abstract

The Fundamental of Multiplying two binary Numbers is the most often use arithmetic operation in the Digital Signal Processor. Therefore, Multiplier design block is especially crucial in VLSI prospectus when Speed and Area is the concern. Many of the Design Topologies regarding this operation has been approached over the years.

Item Type: Final Year Project Report
Additional Information: Project Report (B.Sc.) - Universiti Malaysia Sarawak, 2006.
Uncontrolled Keywords: Binary numbers, multiplier, engineering, research, undergraduate, UNIMAS, Universiti Malaysia Sarawak, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, IPTA, education
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Academic Faculties, Institutes and Centres > Faculty of Engineering
Depositing User: Karen Kornalius
Date Deposited: 21 May 2014 03:08
Last Modified: 03 Sep 2015 08:58
URI: http://ir.unimas.my/id/eprint/2816

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