High Efficiency CMOS Class E Power Amplifier Using 0.13 μm Technology-0

Murad, S.A.Z. and Ahamd, M.F and M. Mohamad, Shahimin and Ismail, R.C and Cheng, K.L and Rohana, Sapawi (2012) High Efficiency CMOS Class E Power Amplifier Using 0.13 μm Technology-0. IEEE Symposium on Wireless Technology and Applications (ISWTA), 2012. ISSN 2324-7843

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Official URL: http://ieeexplore.ieee.org/document/6373883/

Abstract

This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-μm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with on-chip input and output impedance matching. The simulation results indicate that the PA delivers 11.9 dBm output power and 53% power added efficiency (PAE) with 1.3-V power supply into a 50-Ω load. The chip layout is 0.27 mm2.

Item Type: Article
Uncontrolled Keywords: CMOS integrated circuits, Power amplifiers, Power generation, Wireless communication, CMOS technology, Topology, Impedance matching, unimas, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, ipta, education, research, Universiti Malaysia Sarawak
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Academic Faculties, Institutes and Centres > Faculty of Engineering
Depositing User: Karen Kornalius
Date Deposited: 12 Jun 2017 06:19
Last Modified: 12 Jun 2017 06:19
URI: http://ir.unimas.my/id/eprint/16593

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