Design of buffer to drive large capacitive load with minimum delay

Khadijah binti, Usaini (2004) Design of buffer to drive large capacitive load with minimum delay. [Project Report] (Unpublished)

[img]
Preview
PDF
Design of buffer to drive large capacitive load with minimum delay.pdf

Download (595kB) | Preview

Abstract

The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A.

Item Type: Project Report
Additional Information: Project Report (BSc.) - Universiti Malaysia Sarawak, 2004.
Uncontrolled Keywords: UNIMAS, Universiti Malaysia Sarawak, research, undergraduate, engineering, cascade of inverters, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, IPTA, education
Subjects: T Technology > TJ Mechanical engineering and machinery
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Academic Faculties, Institutes and Centres > Faculty of Engineering
Depositing User: Karen Kornalius
Date Deposited: 21 May 2014 02:26
Last Modified: 20 Mar 2015 07:58
URI: http://ir.unimas.my/id/eprint/2805

Actions (For repository members only: login required)

View Item View Item