Murad, S.A.Z. and Md Isa, M.N. and Bakar, F.A. and Sapawi, R. (2016) High efficiency 2.4 GHz CMOS two stages class-F power amplifier for wireless transmitters. Recent Advances in Electrical and Electronic Engineering, 9 (1). pp. 63-67. ISSN 23520965Full text not available from this repository.
A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-μm CMOS process. The proposed class-F PA employs cascade topology. The transistor’s on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm2.
|Uncontrolled Keywords:||Cascade; Class F; Output power; Power added efficiency; Power amplifier; Wireless, unimas, university, universiti, Borneo, Malaysia, Sarawak, Kuching, Samarahan, ipta, education, research, Universiti Malaysia Sarawak|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Divisions:||Academic Faculties, Institutes and Centres > Faculty of Engineering|
|Depositing User:||Karen Kornalius|
|Date Deposited:||24 Jun 2016 02:34|
|Last Modified:||24 Jun 2016 02:34|
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